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| (R) ISL8560 Data Sheet August 17, 2007 FN9244.5 DC/DC Power Switching Regulator The ISL8560 is a step down DC/DC power switching regulator which accepts 9.0V to 60V input and provides a 2A output current. The output voltage can be set in the range between 1.21V and 55V by means of an external divider. The device uses an internal power DMOS transistor with a typical rDS(ON) of 0.19 to obtain very high efficiency and high switching speed. A switching frequency in the range of 100kHz to 600kHz can be realized (the maximum power dissipation of the various packages must be observed). Notable features of this next generation of DC/DC converter includes pulse-by-pulse current limit for FET protection, hiccup mode for short circuit protection, voltage feedforward regulation, Frequency SYNC, soft-start, low standby current of 60A typical in the disabled state, and thermal shut-down. The device is available in a 20 Ld QFN package. Features * Voltage feedforward mode * Step down DC/DC supporting up to 2A * Input voltage range of 9.0V to 60V * Internal reference of 1.21V 1% * Adjustable output voltage range of 1.21V to 55V * Adjustable switching frequency 100kHz to 600kHz * Frequency SYNC pin * Zero load current operation * Pulse by pulse mode current limit and Hiccup mode * Low standby current of 60A typical * Thermal shut-down * Load dump to 100V for 400ms Ordering Information PART NUMBER (Note) ISL8560IRZ PART MARKING TEMP. RANGE (C) PACKAGE (Pb-free) PKG. DWG. # * Pb-free plus anneal available (RoHS compliant) Applications * Industrial and automotive power supplies * Portable computers * Battery chargers * Distributed power systems ISL8560IRZ -40 to +85 20 Ld 6x6 QFN L20.6x6B ISL8560IRZ-T* ISL8560IRZ -40 to +85 20 Ld 6x6 QFN L20.6x6B *Please refer to TB347 for details on reel specifications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Related Literature * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" Pinout ISL8560 (20 LD QFN) TOP VIEW VIN VIN VIN VIN 17 LX 16 15 14 13 12 11 6 SYNC 7 RTCT 8 SGND 9 FB 10 COMP LX SS PGND PGOOD REF 20 LX LX BOOT EN# VCC5 1 2 3 4 5 19 18 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8560 Absolute Maximum Ratings Input Voltage VIN . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 72V Voltage at BOOT pin . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 82V LX, RTCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 60V REF, FB, SS, EN#, SYNC, PGOOD pins. . . . . . . . . . . . . . . . . . . .8V VCC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5.5V Thermal Information Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 30 1.5 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3W Maximum Junction Temperature (Hermetic Package or Die) . . +150C Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Junction Temperature Range. . . . . . . . . . . . . . . . . .-40C to +125C Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 9.0V to 60V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. *An accidental short between VCC5 and GND may cause excessive heating and permanent damage to the device. NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Additional heatsinking may be required to insure that the junction temperature does not exceed above +125C. Electrical Specifications PARAMETER VIN SUPPLY Input Voltage Range VIN SUPPLY CURRENT Shut-down Current Unless otherwise specified the specifications listed in the table are tested at TA = +25C and guard band for the full Temperature Range, VIN = 48V, VOUT = 5.0V, IOUT = 0A. Typical values are at TA = +25C. SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 9.0 24 60 V IDD VIN = 9V, EN = HIGH VIN = 60V, EN = HIGH 35 60 3.6 6.0 60 110 4 8.0 A A mA mA Operating Current IDD VIN = 9V, VFB = 1.5V VIN = 60V, VFB = 1.5V VCC5 SUPPLY (A 1F cap is needed from VCC5 to GND) VCC5 Output Voltage Maximum Output Current INPUT UV Rising UV Threshold UV Threshold Hysteresis BUCK CONVERTER Output Voltage (Note 3) Maximum Duty Cycle Minimum Controllable ON Time OSCILLATOR Total Variation on Set Frequency Frequency Range (Set by RTCT) SYNC Range Tested Oscillation Frequency fOSC fOSC fOSC VOSC VIN = 9V to 60V, RT = 100k, CT = 1200pF VIN = 9V to 60V, RT = 27.4k, CT = 220pF Max Ramp Amplitude VIN = 9V Over the VIN range with frequency set by external resistor and capacitor at RTCT 100 100 60 725 1 10 600 600 % kHz kHz kHz kHz VP IOUT = 2A F = 300kHz F = 300kHz 1.2 90 96 50 VIN - 5 V % ns 7.8 0.18 0.3 8.9 0.55 V V VIN = 9.0V to 60V, IL = 0mA to 5mA VIN = 24V 4.9 5.0 5.1 5 V mA 2 FN9244.5 August 17, 2007 ISL8560 Electrical Specifications PARAMETER Modulator Gain Min OFF Time REFERENCE AND SOFT-START Internal Reference Voltage Soft-Start Current Soft-Start Threshold ERROR AMPLIFIER Transconductance Gain-Bandwidth Product Slew Rate COMP Pin Drive Internal Feedback Voltage Internal Feedback Bias Current OVERCURRENT PROTECTION Dynamic Current Limit ON Time Dynamic Current Limit OFF Time Switch Current Limit POWER GOOD (OPEN DRAIN) Power-Good Lower Threshold VPGVPG+ PGOOD Leakage Current PGOOD Voltage Low MOSFET Switch ON Resistance EN# Input HIGH Level (Asserted) Input LOW Level (Unasserted) Input Current HIGH Input Current LOW SYNC Input HIGH Level (Asserted) Input LOW Level (Unasserted) Input Current HIGH Input Current LOW THERMAL SHUT-DOWN Thermal Shut-down Temperature Thermal Shut-down Hysteresis Rising Threshold 150 15 C C VINHIGH VINLOW ISYNCHIGH ISYNCLOW 2.6 1.2 0.2 0.2 V V A A VINHIGH VINLOW IENHIGH IENLOW VIN = 24V VIN = 24V 2.6 1.2 25 25 V V A A rDS(ON) IOUT = 2A, VBOOT = VIN + 5.0V, Tested at wafer level 0.19 0.355 IPGLKG Fraction of the VOUT set point; ~3s noise filter Fraction of the VOUT set point; ~3s noise filter VPULLUP = 5.5V IPGOOD = 4mA 85 111 89 115 1 0.5 % % A V tOCON tOCOFF ILIMIT TA = +25C 3.2 16 4 4.0 4.8 Clock pulses SS cycle A gm GBW SR ICOMP VFB IFB TA = -40C to +85C, VIN = 9.0V to 60V TA = -40C to +85C, VFB = 1.20V 1.194 3.9 5.7 15 6 200 1.210 50 1.222 100 7.2 mS MHz V/s A V nA VREF ISS VSOFT 8 0.8 1.21 10 12 V A V Unless otherwise specified the specifications listed in the table are tested at TA = +25C and guard band for the full Temperature Range, VIN = 48V, VOUT = 5.0V, IOUT = 0A. Typical values are at TA = +25C. (Continued) SYMBOL VVIN/VOSC TEST CONDITIONS MIN TYP 9 150 300 MAX UNITS ns 3 FN9244.5 August 17, 2007 ISL8560 Pin Descriptions LX (Pins 1, 2, 15, 16) There are four output pins that must be connected together externally in normal operation. SGND (Pin 8) The SGND terminal of the ISL8560 provides the return path for the control and monitor portions of the IC. FB (Pin 9) This is the feedback pin. The feedback ratio is set by an external resistor divider connected to the load. BOOT (Pin 3) A capacitor is connected from this pin to the output pin. An internal 10V supply and an internal schottky diode provide the high side voltage to drive the gate of the output DMOS device. COMP (Pin 10) This pin is connected to the output of the Error Amplifier and is used to compensate the loop. The Error Amplifier is a GM amplifier. EN# (Pin 4) The EN# input will disable the part and shut-down all function when it is held high or left OPEN. The EN# current will be 10A typical. An internal pull-up resistor will hold the pin high. When EN# = Low, the part is enabled. Connect to GND for auto start-up. REF (Pin 11) 1.20V reference output. Bypass to GND with 0.01F capacitor. PGOOD (Pin 12) This pin is an open drain output that is turned on when the feedback voltage is more than 10% from the reference voltage, indicating that the output is not within 10% of set point. VCC5 (Pin 5) VCC5 is the +5.0V output pin which provides an output of an internal supply for supply filtering purposes. A 1F capacitor should be connected from this pin to GND. Internal VDD supply is set at 5.0V (not planned that the user would use this supply). PGND (Pin 13) This pin is used as the ground connection of the power train. SYNC (Pin 6) This pin provides a digital input pin to synchronize the internal oscillator to an external signal. When the sync function is not used, this pin can be left open or tied to GND. If the sync function is used, the RTCT timing must be set to a frequency lower than the sync input frequency. The termination of the ramp is synchronized with the rising edge of the sync input signal. There are no duty cycle restrictions on the input sync signal. Input thresholds are TTL compatible. SS (Pin 14) A capacitor is connected from this pin to GND to determine the soft-start timing. The soft-start pin internal charging current is 10A. VIN (Pins 17, 18, 19, 20) The input supply for the PWM regulator power stage. Connected to DRAIN of the high side MOSFET. RTCT (Pin 7) A resistor to VIN and a capacitor to GND determine the frequency of the saw-tooth oscillator. Resistor range, R = 20k to 100k. Capacitor range, C = 470pF to 1.2nF. The oscillator amplitude will vary from approximately 0.9V to 10V as VIN changes from 8.5V to 60V to maintain constant frequency and provide feed forward. The oscillator will have a fixed off time, which will establish the maximum on time for the regulator. This off time will be <200ns. The maximum duty cycle for a 500kHz system will therefore be approximately 90% as the frequency of the maximum duty cycle will increase (95% for 250kHz system). The minimum duty cycle is zero. 4 FN9244.5 August 17, 2007 ISL8560 REF SS SO FTSTART CO M P RTCT SYNC VCC5 BO O T RAM P G EN O SC LDO EN# FB 3pF 1.6k OVFLT +14% + + -14% 5 + BANDG AP 1.21V + EAM P + PW M CO M P PW M LOG IC CONTRO LLER PRO TECTIO N DRIVER VIN LX PG ND UVFLT O CFLT + CSA PG O O D 3s DELAY SG ND FIGURE 1. BLOCK DIAGRAM OF THE ISL8560 FN9244.5 August 17, 2007 ISL8560 VIN VIN 9V TO 60V VIN + C9 C4 150F 0.1F PGND LX LX BOOT VIN R1 20k C3 1F C1 470pF EN# VCC5 SYNC RTCT SGND SS ISL8560 VIN VIN LX LX C1 0.1F L1 22H + R2 51.1k OUTPUT 5V D1 B2100 C8 470F C7 100pF R6 5.62k PGND PGOOD REF COMP FB R4 301k C6 390pF C10 100pF C11 1F R5 100k VCC5 C5 0.1F R3 16.2k FIGURE 2. TYPICAL SCHEMATIC FOR ISL8560 (5V VOUT) VIN VIN 18V TO 60V VIN C9 150F PGND + C4 0.1F LX LX BOOT VIN R1 20k C1 470pF EN# VCC5 SYNC RTCT SGND SS C5 0.1F ISL8560 VIN VIN LX LX C1 0.1F L1 33H + R2 51.1k OUTPUT 12V C7 330pF R6 5.62k C10 100pF R5 100k VCC5 D1 B2100 C8 470F PGND PGOOD REF COMP FB R4 390k C6 820pF C11 1F C3 1F R3 5.62k FIGURE 3. TYPICAL SCHEMATIC FOR ISL8560 (12V VOUT) 6 FN9244.5 August 17, 2007 ISL8560 Typical Performance Curves 100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 0.0 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 1.8V VOUT 1.2V VOUT EFFICIENCY (%) 2.5V VOUT 3.3V VOUT 5V VOUT 100 90 80 70 60 50 40 30 20 0.0 3.3V VOUT 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 2.5V VOUT 1.8V VOUT 1.2V VOUT 12V VOUT 5V VOUT FIGURE 4. EFFICIENCY vs LOAD (12V INPUT - 500kHz) FIGURE 5. EFFICIENCY vs LOAD (24V INPUT - 500kHz) 100 90 80 EFFICIENCY (%) 70 60 50 40 30 24V VOUT 12V VOUT EFFICIENCY (%) 100 90 80 70 60 50 40 30 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 20 0.0 24V VOUT 12V VOUT 2.5V VOUT 3.3V VOUT 5V VOUT 1.8V VOUT 2.5V VOUT 3.3V VOUT 5V VOUT 1.8V VOUT 20 0.0 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 FIGURE 6. EFFICIENCY vs LOAD (36V INPUT - 500kHz) FIGURE 7. EFFICIENCY vs LOAD (48V INPUT - 500kHz) 3.38 3.35 OUTPUT VOLTAGE (V) 3.32 3.29 36V VIN 3.26 3.23 3.20 0.0 48V VIN 24V VIN 12V VIN OUTPUT VOLTAGE (V) 5.10 5.05 5.00 12V VIN 4.95 4.90 4.85 4.80 0.0 36V VIN 48V VIN 24V VIN 0.5 1.0 1.5 2.0 2.5 0.5 1.0 1.5 2.0 2.5 OUTPUT LOAD (A) OUTPUT LOAD (A) FIGURE 8. VOUT REGULATION vs LOAD (VOUT = 3.3V - 500kHz) FIGURE 9. VOUT REGULATION vs LOAD (VOUT = 5V - 500kHz) 7 FN9244.5 August 17, 2007 ISL8560 Typical Performance Curves (Continued) 12.30 12.20 OUTPUT VOLTAGE (V) 12.10 24V VIN 12.00 11.90 11.80 11.70 0.0 36V VIN 48V VIN OUTPUT VOLTAGE (V) 24.4 24.3 24.2 24.1 24.0 23.9 23.8 0.0 48V VIN 36V VIN 0.5 1.0 1.5 2.0 2.5 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 OUTPUT LOAD (A) FIGURE 10. VOUT REGULATION vs LOAD (VOUT = 12V - 500kHz) FIGURE 11. VOUT REGULATION vs LOAD (VOUT = 24V - 500kHz) 3.0 POWER DISSIPATION (W) 2.5 36V VIN 2.0 1.5 1.0 24V VIN 0.5 0.0 0.0 12V VIN 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 48V VIN POWER DISSIPATION (W) 3.0 2.5 36V VIN 2.0 1.5 1.0 24V VIN 0.5 0.0 0.0 12V VIN 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 48V VIN FIGURE 12. POWER DISSIPATION vs LOAD (VOUT = 3.3V - 500kHz) FIGURE 13. POWER DISSIPATION vs LOAD (VOUT = 5V - 500kHz) 3.0 POWER DISSIPATION (W) 2.5 36V VIN 2.0 1.5 1.0 24V VIN 0.5 0.0 0.0 48V VIN POWER DISSIPATION (W) 3.0 2.5 36V VIN 2.0 1.5 1.0 0.5 0.0 0.0 48V VIN 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 0.5 1.0 OUTPUT LOAD (A) 1.5 2.0 FIGURE 14. POWER DISSIPATION vs LOAD (VOUT = 12V - 500kHz) FIGURE 15. POWER DISSIPATION vs LOAD (VOUT = 24V - 500kHz) 8 FN9244.5 August 17, 2007 ISL8560 Typical Performance Curves (Continued) 3.4 3.4 OUTPUT VOLTAGE (V) 3.3 3.3 1A LOAD 3.3 3.2 3.2 NO LOAD 2A LOAD OUTPUT VOLTAGE (V) 5.10 5.05 5.00 IOUT = 1A 4.95 4.90 4.85 4.80 IOUT = 2A IOUT = 0A 5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN (PWM MODE) FIGURE 17. OUTPUT VOLTAGE REGULATION vs VIN (VOUT = 5V - 500kHz) 12.3 12.2 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 12.1 IOUT = 1A 12.0 11.9 11.8 11.7 IOUT = 0A 24.75 24.50 IOUT = 1A 24.25 24.00 IOUT = 2A 23.75 23.50 23.25 IOUT = 0A IOUT = 2A 5 15 25 35 45 55 65 75 5 15 25 35 45 55 65 75 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 18. OUTPUT VOLTAGE REGULATION vs VIN (VOUT = 12V - 500kHz) FIGURE 19. OUTPUT VOLTAGE REGULATION vs VIN (VOUT = 24V - 500kHz) LX = 10V/DIV 900 POWER DISSIPATION (mW) 800 700 600 500 400 300 200 100 0 5 15 25 35 45 55 65 75 IOUT = 0A RTCT = 2V/DIV VOUT RIPPLE = 50mV/DIV IL = 0.2A/DIV VIN (V) FIGURE 20. POWER DISSIPATION vs VIN AT NO LOAD (VOUT = 5V - 5000kHz) FIGURE 21. STEADY STATE OPERATION AT NO LOAD 9 FN9244.5 August 17, 2007 ISL8560 Typical Performance Curves (Continued) LX = 10V/DIV VOUT RIPPLE = 50mV/DIV IL = 1A/DIV RTCT = 2V/DIV LX = 10V/DIV VOUT RIPPLE = 50mV/DIV IL = 0.2A/DIV FIGURE 22. STEADY STATE OPERATION WITH FULL LOAD FIGURE 23. LOAD TRANSIENT EN = 5V/DIV EN = 5V/DIV VOUT = 2V/DIV PRE-BIASED WITH 4V VOUT = 1V/DIV SS = 2V/DIV SS = 2V/DIV IL = 0.5A/DIV IL = 0.5A/DIV FIGURE 24. SOFT-START AT NO LOAD FIGURE 25. SOFT-START WITH PRE-BIASED EN = 5V/DIV VOUT = 2V/DIV IL = 1A/DIV LX = 10V/DIV SS = 2V/DIV IL = 2A/DIV VOUT = 2V/DIV PGOOD = 5V/DIV FIGURE 26. SOFT-START AT FULL LOAD FIGURE 27. OUTPUT SHORT CIRCUIT 10 FN9244.5 August 17, 2007 ISL8560 Typical Performance Curves (Continued) LX = 10V/DIV VOUT = 2V/DIV IL = 2A/DIV PGOOD = 5V/DIV FIGURE 28. OUTPUT SHORT CIRCUIT Applications Information Product Description The ISL8560 is a non-synchronous, integrated FET 2A stepdown regulator which operates from an unregulated input of 9V to 60V. The output voltage is user-adjustable with a pair of external resistors. Frequency of operation is adjustable from 100kHz to 600kHz set by RTCT. An external signal with higher frequency can be injected to SYNCH to synchronize the controller. The buck controller drives an internal N-Channel MOSFET and requires an external diode to deliver load current up to 2A. A Schottky diode is recommended for improved efficiency and performance over a standard diode. The converter output is regulated down to 1.21V from an input source. The PWM control loop uses a single output voltage loop with input voltage feed forward which simplifies feedback loop compensation and rejects input voltage variation. External feedback loop compensation allows flexibility in output filter component selection. The buck regulator is equipped with a lossless current limit scheme. The current limit in the buck regulator is achieved by monitoring the drain-to-source current of the internal switching power MOSFET. The current limit threshold is internally set at 4.5A peak. Additional feature includes programable soft-start to support proper start up of wide output capacitance range. voltage is gradually increased to ensure proper soft-start operation. When the EN# reaches logic LOW, the regulator repeats the start-up procedure, including the soft-start function. Connect a capacitor from SS pin to ground. This capacitor, along with an internal 10A current source sets the soft-start interval of the converter, tSS. C SS [ F ] 8.3 t SS [ s ] (EQ. 1) Operating Frequency The ISL8560 can operate at switching frequencies from 100kHz to 600kHz. A resistor tied from the RTCT pin to VIN and a capacitor from RTCT to GND are used to program the switching frequency through the following equation. 6.25 1000 C 1 [ nF ] = ---------------- ----------------------------- - 0.3 R [ k ] f OSC [ kHz ] (EQ. 2) Caution: When the ISL8560 is in disabled state, the voltage across RTCT pin will reach VIN voltage. Make sure that the voltage rating of the RTCT capacitor is rated as high as the input voltage. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to Figure 30. The output voltage programming resistor, R3, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 1k and 10k. R 2 x 1.21V R 3 = ------------------------------------V OUT - 1.21V (EQ. 3) Start-Up and Shut-Down When the EN# pin is connected to a logic high, the ISL8560 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 110A. When the EN# pin is tied to GND, and VIN reaches approximately 9V, the regulator begins to switch. The output If the output voltage desired is 1.21V, then R3 is left unpopulated. FN9244.5 August 17, 2007 11 ISL8560 Fault Protection The ISL8560 monitors the output of the regulator for overcurrent and undervoltage events. The ISL8560 also provides protection from excessive junction temperatures. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. The shape of the output voltage waveform during a load transient that represents the worst case loading conditions will ultimately determine the number of output capacitors and their type. When this load transient is applied to the converter, most of the energy required by the load is initially delivered from the output capacitors. This is due to the finite amount of time required for the inductor current to slew up to the level of the output current required by the load. This phenomenon results in a temporary dip in the output voltage. At the very edge of the transient, the Equivalent Series Inductance (ESL) of each capacitor induces a spike that adds on top of the existing voltage drop due to the Equivalent Series Resistance (ESR). After the initial spike, attributable to the ESR and ESL of the capacitors, the output voltage experiences sag. This sag is a direct consequence of the amount of capacitance on the output. During the removal of the same output load, the energy stored in the inductor is dumped into the output capacitors. This energy dumping creates a temporary hump in the output voltage. This hump, as with the sag, can be attributed to the total amount of capacitance on the output. Figure 29 shows a typical response to a load transient. Overcurrent Protection The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFETs. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from LOW to HIGH. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are seven sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result with the regulator attempting to restart in a hiccup mode with the delay between restarts being 4 soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away prior to the OC fault counter reaching a count of four, the overcurrent condition flag will set back to LOW. If the overcurrent condition flag is HIGH and the overcurrent fault counter is less than four and an undervoltage event is detected, the regulator will be shut down immediately. Undervoltage Protection If the voltage detected on the FB pin falls 14% below the internal reference voltage and the overcurrent condition flag is LOW, then the regulator will be shut down immediately under an undervoltage fault condition. An undervoltage fault condition will result with the regulator attempting to restart in a hiccup mode with the delay between restarts being 4 softstart periods. At the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. VHUMP VOUT Thermal Protection If the ISL8560 IC junction temperature reaches a nominal temperature of +150C, the regulator will be disabled. The ISL8560 will not re-enable the regulator until the junction temperature drops below +135C. VESR VSAG VESL Output Capacitor Selection An output capacitor is required to filter the inductor current and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. IOUT Itran FIGURE 29. TYPICAL TRANSIENT RESPONSE 12 FN9244.5 August 17, 2007 ISL8560 The amplitudes of the different types of voltage excursions can be approximated by using the formulas in Equation 4: V ESR = ESR * I tran 2 dI tran V ESL = ESL * --------------dt Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. Use I of approximately 30% of IOUT is a good compromise. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL8560 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. Equation 8 gives the approximate response time interval for application and removal of a transient load: tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT (EQ. 8) L out * I tran V SAG = ------------------------------------------------C out * ( V in - V out ) L out * I tran V HUMP = ------------------------------C out * V out 2 (EQ. 4) where Itran = Output Load Current Transient Cout = Total Output Capacitance In a typical converter design, the ESR of the output capacitor bank dominates the transient response. The ESR and the ESL are typically the major contributing factors in determining the output capacitance. The number of output capacitors can be determined by using the following equation that relates the ESR and ESL of the capacitors to the transient load step and the voltage limit (Vo): ESL * dI tran --------------------------------- + ESR * I tran dt Number of Caps = ----------------------------------------------------------------------V o (EQ. 5) If VSAG and/or VHUMP are found to be too large for the output voltage limits, then the amount of capacitance may need to be increased. In this situation, a trade off between output inductance and output capacitance may be necessary. The ESL of the capacitors, which is an important parameter in Equations 4 and 5, is not usually listed in databooks. Practically, it can be approximated if an impedance vs frequency curve is given for a specific capacitor (C): 1 ESL = ---------------------------------------2 C ( 2 * * f res ) (EQ. 6) where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Rectifier Selection Current circulates from ground to the junction of the MOSFET and the inductor when the high-side switch is off. As a consequence, the polarity of the switching node is negative with respect to ground. This voltage is approximately -0.5V (a Schottky diode drop) during the off time. The rectifier's rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor. The power dissipation is: V OUT P D [ W ] = I OUT V D 1 - --------------- V IN where fres is the frequency where the lowest impedance is achieved (resonant frequency). The ESL of the capacitors becomes a concern when designing circuits that supply power to loads with high rates of change in the current. (EQ. 9) Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by Equation 7: I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR (EQ. 7) where VD is the voltage of the Schottky diode = 0.5V to 0.7V Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the VIN's pin. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time the upper MOSFET turns on. Place the small ceramic capacitors physically close to the VIN and PGND pins. The important parameters for the bulk input capacitance are the voltage rating and the RMS current rating. For reliable 13 FN9244.5 August 17, 2007 ISL8560 operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. Their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a conservative guideline. For most cases, the RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. The maximum RMS current through the input capacitors may be closely approximated through Equation 10: 2 V OUT V OUT 2 1 V IN - V OUT V OUT ------------- x I OUT x 1 - ------------- + ----- x ---------------------------- x ------------- 12 L x f V IN V IN V IN MAX OSC OSC PWM COMPARATOR VOSC DRIVER VIN LX DRIVER D LO CO VOUT - + ZFB VE/A + ESR (PARASITIC) - ZIN REFERENCE ERROR AMP DETAILED COMPENSATION COMPONENTS C10 C6 R4 ZFB ZIN C7 R2 FB R3 R6 VOUT (EQ. 10) For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested. COMP gm + ISL8560 REFERENCE Feedback Compensation Figure 30 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the LX node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at fLC and a zero at fESR . The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC . The ISL8560 incorporates a feed forward loop that accounts for changes in the input voltage. This maintains a constant modulator gain. R 2 V OUT = 1.20 x 1 + ------ R 3 FIGURE 30. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN AND OUTPUT VOLTAGE SELECTION Figure 30. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R3gm/(R2+R3) for desired converter bandwidth. 2. Place 1ST Zero Below Filter's Double Pole (~75% fLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error transconductance's OpenLoop Gain. 7. Estimate Phase Margin - Repeat if Necessary. Modulator Break Frequency Equations 1 f LC = -----------------------------------------2 x L O x C O 1 f ESR = ------------------------------------------2 x ESR x C O (EQ. 11) The compensation network consists of the transconductance amplifier (internal to the ISL8560) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180. The equations in the following section relate the compensation network's poles, zeros and gain to the components (R2, R3 , R4 , R6, C10 , C6, and C7) in 14 FN9244.5 August 17, 2007 ISL8560 Compensation Break Frequency Equations 1 f Z1 = --------------------------------------------------------( R4 gm + 1 ) 2 --------------------------------- C 6 gm 1 f Z2 = -------------------------2R 2 C 7 1 f P1 = -------------------------2R 6 C 7 (EQ. 12) 1 f P2 = ----------------------------2R 4 C 10 Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently between 100kHz and 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes these voltage spikes. As an example, consider the turn-off transition of the control MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the freewheeling Schottky diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in the ISL8560 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. Assumption: R6< VIN VIN CIN ISL8560 L CBP2 VCC5 LX D COUT1 LOAD VOUT1 20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN COMP C6 R4 PGND FB R3 GND PAD KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER VIA CONNECTION TO GROUND PLANE C10 R2 C7 R6 FREQUENCY (Hz) FIGURE 31. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN A more detailed explanation of voltage mode control of a buck regulator can be found in Tech Brief TB417, titled "Designing Stable Compensation Networks for Single Phase Voltage Mode Buck Regulators." FIGURE 32. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 15 FN9244.5 August 17, 2007 ISL8560 A multi-layer printed circuit board is recommended. Figure 32 shows the connections of the critical components in the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually a middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the LX terminals to the output inductor short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the LX nodes. Use the remaining printed circuit layers for small signal wiring. In order to dissipate heat generated by the internal LDO and other power components, the ground pad at the bottom of the device should be connected to the ground plane through at least nine vias. This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL8560 first. Minimize the length of the connections between the input capacitors, CIN. Make the PGND and the output capacitors as short as possible. NOTE: It is recommended that any applications with input voltage greater than 30VDC should be polymer coated to meet Intersil's IPC-2221 creepage and clearance specification. 16 FN9244.5 August 17, 2007 ISL8560 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L20.6x6B 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJB ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.635 0.50 3.33 3.33 0.28 MIN 0.80 NOMINAL 0.90 0.20 REF 0.33 6.00 BSC 5.75 BSC 3.43 6.00 BSC 5.75 BSC 3.43 0.80 BSC 0.60 20 5 5 0.60 12 0.70 0.15 3.53 3.53 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 0 12/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN9244.5 August 17, 2007 |
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